The present invention relates to a semiconductor device manufacturing method and an ion implanter used therein, and more particularly relates to method for manufacturing a semiconductor device that includes a capacitor insulating film to which ion implantation is performed.
Recently, gate insulating films become thinner in association with miniaturization of elements in semiconductor devices, and therefore, liabilities for damage and dielectric breakdown of the gate insulating films by charge-up in process increase. Among of all, charge-up caused by plasma etching, plasma CVD, and ion implantation presents significant problems in process.
Referring to the ion implantation, an ion beam electrified positively is implanted directly into a semiconductor element or a semiconductor substrate, so that the surface portion of the semiconductor element is liable to be electrified positively. Particularly, if the gate insulating film is very thin, dielectric breakdown is liable to be caused in the gate insulating film by the positive charge-up. Further, if the area of an electrode portion called antenna for collecting charge is large, the surface potential of the semiconductor element is liable to rise for much charge are collected. When the collected charge exceeds a given amount and further exceeds the amount of charge to breakdown Qbd inherent to the gate insulating film, dielectric breakdown is caused (for example, see “Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrode in Wafer Processing,” by Hiroko Kubo et al., IEICE Transactions on Electronics, Vol. E79-C No. 2, pp. 198-205, February, 1996).
The dielectric breakdown by an ion beam is more liable to be caused as the beam current density is higher. Also, it is known that breakdown by charge-up is more liable to be caused as acceleration energy for ions at ion implantation is higher. Under the circumstances, a method of preventing the dielectric breakdown has been proposed in which conditions for ion implantation are set so that an acceleration energy and a beam current become equal to or lower than an amount of charge to breakdown Qbd of a gate insulating film in order not to cause the breakdown by charge-up (for example, see Japanese Patent Application Laid Open Publication No. 7-221306A, which is referred hereinafter to as Patent Document 1).
Further, there are known methods using various electron flood guns for supplying electrons for neutralizing positive charge onto a semiconductor element in order to prevent the positive charge-up by ion beams. However, it is further known that the electron flood guns supply negative charge to the surface of the semiconductor element, similar to the ion beams, to cause negative electrification of the surface portion to the contrary, inviting dielectric breakdown by the negative charge-up. Under the circumstances, a technique has been reported in which the negative charge-up by electrons from an electron flood gun in the surface portion of a semiconductor element is suppressed so that the charge-up amount is controlled at a value equal to or smaller than the breakdown voltage by controlling the energy of the electrons from the electron flood gun (for example, see Japanese Patent Publication No. 3202002B, which is referred hereinafter to as Patent Document 2).
Though the dielectric breakdown of the gate insulating films can be obviated by suppressing the negative charge-up by the electron flood gun, it is still awkward to say that the other dielectric breakdown of the gate insulating films, which is caused due to the positive charge-up by the ion beams, is prevented completely. The positive charge-up depends on an electron neutralization mechanism by the electron flood gun relative to the ion beam used for ion implantation, and the charge-up neutralization depends on not only the beam current, the acceleration energy, and the like but also beam scanning speed and the like.
The present inventors have found that the charge-up state caused due to ion beams rather differs depending on the beam scanning speed. The beam scan methods includes various methods such as: a method in which an ion beam scans two-dimensionally on the X-Y plane electrostatically or electromagnetically with a substrate fixed; a method in which the ion beam scans the substrate one-dimensionally and electrostatically or electromagnetically while a semiconductor substrate is scanned mechanically and one-dimensionally in a direction perpendicular to the scanning direction of an ion beam; a method in which radial direction (r) to rotation direction (θ) scan is performed to a wafer placed and rotated on a rotary disk one-dimensionally in the radial direction of the disk with an ion beam fixed; a method in which a semiconductor wafer is scanned in the X-Y direction mechanically with an ion beam fixed; and so on. Wherein, the relative line velocity of the ion beam and the semiconductor wafer differs largely among the methods. In this way, the scanning speed ranges wide from extremely low-speed scan to extremely high-speed scan, and therefore, a scheme for suppressing the positive charge-up with no dependency on the scanning speed and the scan method is demanded.